The present invention relates to complimentary metal oxide semiconductor (CMOS) devices, and more specifically, to CMOS devices including a PFET having a hetero channel.
Conventional CMOS devices typically include one or more pairs of complementary and symmetrical p-type field effect transistors (pFETs) and n-type field effect transistors (nFETs) for providing high noise immunity and low static power consumption. CMOS devices utilizing semiconductor devices including one or more semiconductor fins (i.e., FinFETs) can realize an improvement in device performance. Adjusting the fin height and/or fin width may also control current output provided by the FinFET. Forming one or more hetero fins (e.g., fins formed from silicon germanium on a silicon substrate) corresponding to a p-type FinFET results in higher hole mobility through the fin due to the light hole effective mass. However, fabricating CMOS devices including both hetero channels and non-hetero channels require additional masking and etching processes that result in an overall complex and expensive fabrication process.